1. Field of Use
This invention relates to memory systems and more particularly to transfers of multiple words of data by a memory system to a requesting unit (i.e., burst mode).
2. Prior Art
It is well known to construct memory systems from a number of modules. In certain systems, memory modules are paired together to provide a double word fetch access capability (i.e., access a pair of words at a time during a memory cycle of operation).
Such systems are designed to include a burst mode transfer capability wherein a memory controller, which connects in common to a system bus, can deliver groups of multiple words accessed simultaneously over a series of bus cycles without incurring communication delays. U.S. Pat. Nos. 4,366,539 and 4,370,712 describe this type of system.
This capability has been incorporated into high performance microprocessors, such as the Intel 80486 microprocessor. Such burst mode operations are carried out on the microprocessor's synchronous local bus according to a predetermined bus protocol and requires only a single clock cycle per word transfer. To take advantage of this high speed burst mode, it has been proposed to have the microprocessor's main memory structured to be 64 bits wide. In this case, the initial access to memory would require wait state while the subsequent accesses are already present. The third and fourth accesses of the burst each then utilize the clocked page mode mechanism to achieve zero wait states. This proposal is discussed in an article entitled, "The 80486: A Hardware Perspective", by Ron Santore, Byte Magazine, Fall 1989.
While in theory this seems possible, it has been found that at higher speeds, such as 33 MHz, when the memory normally is clocked on the same edges of the system clock signal as the microprocessor, it still requires at least one wait state to occur between successive double word fetches, in order to generate the minimum precharge times required for reliable memory operation. This is due to the necessity to regenerate successive synchronously generated column address strobe (CAS) timing signals for meeting this requirement. Hence, an additional clock time is required. Also, the arrangement proposed in the article specifies the use of very high speed components, such as 60 nanosecond memory chip parts which were not commercially available at the time and today are not commercially available in large quantities.
Accordingly, it is a primary object of the present invention to enable the execution of a burst read operation by a memory unit at a rate which does not reduce system performance.